In this meeting the project was explained - its goals and how they were going to be acheived.
They plan on using the DE-10 Nano to synthesize the CPU design to an FPGA.
The large project group was split into sub teams each that would work on a subsection of the project: CPU Design, Cache and memory design, and Operating system/Compiler team
This meeting the OS and compiler went over how software makes request of the hardware though the kernel.
They brainstormed the requirements the OS would have of the actual CPU.
The hardware team setup Aldec, the VHDL development environment on the member’s PC’s.
They also selected Risc OS as the operating system that the CPU would run.
Before spring break, they used a raspberry pi to run DOOM!
The CPU team went over how to create logic gates and multiplexers in VHDL.
The memory team went over the basic structure of how CPU caches are designed as well as how the project will construct the CPU’s cache.
The teams went over how we will construct the cache.
The team selected the direct caching method as well as how the CPU will transfer blocks of memory from memory to CPU’s upper levels of cache.
The cache team began constructing the layered cache system.
The CPU team designed a full 16 bit Adder, in order to better understand more complicated VHDL projects .
This meeting served as a wrap up of the project for Spring 2023.
Everything that was completed was summarized as well as everything that the members' learned.